Re: further newsbit on those new IBM transistors

From: Carl Feynman (
Date: Tue Jun 26 2001 - 15:08:13 MDT

Brian Atkins wrote:

> My (limited) understanding is that the
> clock signal is transported through a chip layout in order to "trigger"
> the transistors to switch.

Not every transistor has a clock input. Typically there are between four
and ten unclocked transistors in series, and then a "latch", which is a
pair of transistors that switch synchronously with the clock. It is up to
the chip architect to decide how many transistors there are between
latches, and then the logic of the chip has to be designed to fit that
constraint. If you want to be fancy, the architect can decide that part of
the chip will have 10 transistors between latches, and run at 1 GHz, and
part will have five transistors between stages, and run at 2 GHz.

> According to what you are saying it would
> mean there would be only one possible clock speed for a given chip
> design. i.e. if you have 10ghz transistors and parts of the chip use
> 10 transistors in series, then the chip is sold as a 1ghz part.

This is exactly what happens.

> This
> clearly isn't the case since chips are sold in a wide range of speeds.

I'm puzzled by what you mean here. Let me take a stab at it...

Some Pentiums are fast, some Pentiums are slow, but this is because they
are manufactured using different processes, and in some cases, using
different logic designs. From an engineering point of view, they are not
"one chip sold in a wide range of speeds." They are different chips, that
are all labeled "the same" by the marketing department.

You can make a chip run faster by upping the input voltage, as you say, and
also by cooling it. But these modifications typically produce less than a
50% gain, and aren't what account for the speed differences between
different versions of the "same chip". Changes in voltage and temperature
give the engineers that designed the chip the heebie-jeebies, and are not a
robust way of improving performance.

> I think that the chip can be configured to run the clock lines at a
> wide variety of speeds, and the only limitations come in from the fact
> that the transistors may require higher voltage levels to be able to
> switch quickly enough. Higher voltages eventually run you into heat
> dissipation and other problems, putting an upper limit on how fast a
> given chip design/substrate combo can operate.

Actually, chips are usually run near their maximum tolerable voltage. The
limit is set by various kinds of short-circuts being induced by electrons
arcing across a gap or tunneling through an insulator. Heat disspation is
a problem for the packaging engineer. At the high end, we're not pushing
the limits of cooling technology.

I designed chips for supercomputers from '84 to '92, so what I say above is
nine years out of date. But I don't think much has changed.


This archive was generated by hypermail 2.1.5 : Wed Jul 17 2013 - 04:00:36 MDT