From: Brian Atkins (email@example.com)
Date: Tue Jun 26 2001 - 13:48:11 MDT
Dani Eder wrote:
> > chips with 100ghz speeds sometime in 2003. These
> > chips are currently used
> You need to keep clear the distinction between the
> transistor switching speed, which may be 100 GHz,
If you read the article, they say the switching speed is up to 210ghz.
So I don't think the article's claim of 100ghz clock speeds is totally
bogus. High gigahertz speeds are already used for instance in RF chip
components where the chip has to generate microwave radio signals. I'd
have to check to be sure, but I think 5ghz+ clock speeds in SiGe chips
are commonplace nowadays.
> and the chip clock speed, which is the transistor
> speed divided by the number of transistors in series
> involved in one clock cycle. The very shortest
> cycle would be a flip-flop type oscillator, which
> would take 2 transistors. More typically it would
> take 5-10 transistors in series to complete a logic
I am not sure this is correct. My (limited) understanding is that the
clock signal is transported through a chip layout in order to "trigger"
the transistors to switch. According to what you are saying it would
mean there would be only one possible clock speed for a given chip
design. i.e. if you have 10ghz transistors and parts of the chip use
10 transistors in series, then the chip is sold as a 1ghz part. This
clearly isn't the case since chips are sold in a wide range of speeds.
I think that the chip can be configured to run the clock lines at a
wide variety of speeds, and the only limitations come in from the fact
that the transistors may require higher voltage levels to be able to
switch quickly enough. Higher voltages eventually run you into heat
dissipation and other problems, putting an upper limit on how fast a
given chip design/substrate combo can operate.
> Another complication is that modern chips may have
> internal units running at different speeds than the
> external clock. If I recall the fixed point
> unit in the P4 processor actually runs at _twice_
> the clock rate, and some chips run the L1 and L2
> caches at less than the external clock rate.
> Communication with main memory is around 1/10 the
> clock rate.
Exactly, so you see the clock rate is very controllable. The problem I
see with 100ghz chips is that at that speed the electrical signals
actually can't travel very far. Even in the P4, Intel had to design it
so that it sometimes spends multiple clock cycles simply moving data
from one side of the chip to the other. This is one of the reasons that
the P4 gets lower IPC (instructions per clockcycle) than the P3. So
100ghz chips will require most likely a completely new design ethic.
Not to mention as you say the problem of accessing memory, etc. I read
an article in Wired mag a few years ago about how there are companies
working to integrate optical transport methods into motherboard buses-
but I haven't heard much lately.
-- Brian Atkins Director, Singularity Institute for Artificial Intelligence http://www.singinst.org/
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