Re: Jaron Lanier

From: Yan King Yin (
Date: Sat Nov 29 2003 - 13:18:37 MST

--------- Original Message ---------
From: Eugen Leitl <>

>I'm not complaining. We have MPI, nanokernels, architectures
>like Blue Gene (<>
>demonstrates an application, and cites architecture papers),
>coarse-grain FPGA+embedded memory+signalling fabric as
>well as fine-grained cellular architectures. MRAM is only
>a couple of years remote from the marketplace, spintronics
>is soon to follow, molecular memory and cellular logic is
>10-20 years away.

There's 1 more question: Will the von Neumann
architecture be sufficient for running large-scale
neural networks, or is the bottleneck so severe
that a paradigm shift is required?

If fault tolerance can be easily built into memories,
with conventional logic operating on them, can this be

Say a brain-equivalent NN will require about 150Tb of
memory (assume 1 synapse = 1 byte). And assume that
any address is connected to a fraction of this 150Tb
and has to be updated continually on the ms time
scale. We can estimate the bandwidth on the
data/address bus required for this amount of
processing and see if it can be met.


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