Re: Jaron Lanier

From: Eugen Leitl (
Date: Fri Nov 28 2003 - 14:39:13 MST

On Wed, Nov 26, 2003 at 07:11:11PM -0500, Perry E.Metzger wrote:

> Actually, most CPUs sold today do SIMD of various kinds for doing
> multimedia work. There are a lot of easy parallel algorithms in things

Most MMX does indeed *Single Instruction* on Multiple (64-128 bit
registers, seen as array of 32, 16, 8-bit data types). It is a specific
type of parallelism (not MIMD), and it still has to be applied sequentially
on ~10^9 cells, using about 6 GByte/s throughput in best case (sequential
stream with prefetch).

There are about 10^10 switches in a normal PC. A simple CPU takes
some 10^4 switches to implement. A computational cell with nontrivial
functionality some 10^2..10^3. We could have 10^6..10^8 concurrent
locally-coupled (with global connectivity emulation by packet switched
networks) systems on our current PC hardware. Considerably more,
if we talk WSI with 99% yield (defect-tolerant cellular architectures).

> like graphics, and modern processors take advantage of that. Modern
> supercomputers tend to be massively parallel, too. All weather

There's a world of two cultures: XML over wire, and MPI. These two
do not seem to mix.

> prediction is done on such machines. Furthermore, even standard
> computation is done these days by pipelining techniques that
> essentially turn single processors into mildly (say, eight way)
> parallel devices.

Actually pipelining is an abomination. It assumes low-novelty
code, and has terrible costs in hardware and initialisation.

The payoff of tight code and no MMU nor BPU nor pipelining would
be quite dramatic.

Of course, nobody is writing tight code these days.
> The issue is the use of highly non-Von Neumann like architectures for
> every day use. Generally speaking, we haven't found comfortable
> programming models or applications for such beasts.

I find this deeply disconcerting. Don't you?

-- Eugen* Leitl leitl
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